1. Field of the Invention
The present invention relates to a control circuit for a memory array which receives digital signals of a field conforming to any of the conventional television standards and delivers them at an increased field rate, preferably at twice the field rate. The memory array thus serves to produce a flicker-free picture on the screen of a television receiver for conventional television standards, such as PAL or SECAM or NTSC in the respective variants. By reading the signals out of the memory array at an increased field rate and, of course, an increased line rate, large area flicker and line flicker are reduced considerably.
2. Description of the Prior Art
If commercially available random-access memories (RAMs) of 256 kilobytes, i.e., 2.sup.18 bits, are used to store a television field, several such RAMs are necessary. Thus, their number must be reduced to a justifiable measure by carrying out a data reduction prior to the storage, which must be followed by a corresponding increase after readout from the memory array.
Circuits suited for this purpose are described, for example, in Offenlegungsschrift DE 34 17 139 Al, in the pre-published Patent Application EP-A 197 165, in the prior European Application 86 10 5444.3, and the periodicals "ICC '84 Links for the Future", IEEE International Conference on Communications, 1984, Vol. 1, pp. 250-255, "Proceedings of the IEEE", 1985, pp. 592-598, and "Elektrisches Nachrichtenwesen", 1984, pp. 447-449. The data reduction encoder and the data reduction decoder each have a line memory for the video signal included in a scanning line.